Abstract:
Since the invention of the integrated circuit in 1958, the integration of exponentially more devices onto a single chip has transformed computing—yet memory remains largely separated from logic, resulting in a “memory wall”. Recent advances in memory research have introduced a variety of new memory technologies. My research focus, Memory Integration and Data Dis-Aggregation (MIDDAS), envisions a future where massive, diverse memories are physically integrated yet functionally store disaggregated data.
MIDDAS encompasses a continuous spectrum of memory characteristics. This is exemplified by BRIDGE (Blended Retention-Indexed Diverse Gain cEll), a gain cell memory platform developed in my PhD research. The 2-transistor (2T) gain cell memory offers high density and CMOS integration compatibility. By introducing oxide semiconductor (OS) transistors with ultra-low leakage current (< 1e-17 A/μm), BRIDGE expands the design space to support retention times spanning microseconds to seconds. BRIDGE is demonstrated on fabricated N40 CMOS+X monolithic 3D integration chip with Atomic-Layer-Deposited (ALD) Indium Tin Oxide (ITO) FET. Hybrid gain cell (OS-Si) demonstrates 3x density and lower energy compared to high-density (HD) SRAM, scalable to N5 and beyond. Furthermore, integrating gain cells with non-volatile memories (e.g., RRAM) unlocks synergistic system-level benefits from device-circuit-architecture co-design, embodying the “1+1>2” philosophy where diverse memory technologies collaboratively enhance system functionality through integration.
MIDDAS repositions memory as a scalable, intelligent toolbox for AI-era computing, capitalizing on the predictability of memory access, bridging device innovation with software demands.
Bio:
Shuhan Liu is a PhD candidate at Stanford University, advised by H.-S. Philip Wong. She earned B.S. degree from Peking University in 2020. She received 2024 IEEE EDS PhD Fellowship and 2024 IEEE IEDM Best Student Paper Award.
